DK-DEV-5SGXEA7N【PDF 95/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51005

2014.01.10

PLL Cascading

4-25

? Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference

clock source

? Compensate clock network delay

? Zero delay buffering

? Transmit clocking for transceivers

PLL Cascading

Stratix V devices support two types of PLL cascading.

PLL-to-PLL Cascading

This cascading mode synthesizes a more precise output frequency than a single PLL in integer mode.

Cascading two PLLs in integer mode expands the effective range of the pre-scale counter, N and the multiply

counter, M .

Stratix V devices use two types of input clock sources.

? The adjpllin input clock source is used for inter-cascading between fracturable fractional PLLs.

? The cclk input clock source is used for intra-cascading within fracturable fractional PLLs.

Altera recommends using a low bandwidth setting for the source (upstream) PLL and a high bandwidth

setting for destination (downstream) PLL.

Counter-Output-to-Counter-Output Cascading

This cascading mode synthesizes a lower frequency output than a single post-scale counter, C . Cascading

two C counters expands the effective range of C counters.

PLL External Clock I/O Pins

Two adjacent corner and center fractional PLLs share four dual-purpose clock I/O pins, organized as one

of the following combinations:

? Four single-ended clock outputs

? Two single-ended outputs and one differential clock output

? Four single-ended clock outputs and two single-ended feedback inputs in the I/O driver feedback for

zero delay buffer (ZDB) mode support

? Two single-ended clock outputs and two single-ended feedback inputs for single-ended external feedback

(EFB) mode support

? One differential clock output and one differential feedback input for differential EFB support (only one

of the two adjacent fractional PLLs can support differential EFB at one time while the other fractional

PLL can be used for general-purpose clocking)

Note: All left and right fractional PLLs in Stratix V devices do not support external clock outputs.

The following figure shows that any of the output counters ( C[0..17] ) or the M counter on the PLLs can

feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins

available from a given PLL.

Clock Networks and PLLs in Stratix V Devices

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